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RF Engines' ChannelCore64 now available

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RF Engines
: 20 April, 2007  (New Product)
RF Engines' ChannelCore64 now available optimised for Xilinx Virtex4
Achieving 64 reconfigurable DDC Channels in one FPGA

RF Engines has optimised its ChannelCore64 for the Xilinx

Virtex4 FPGA.

This fully flexible 64-channel digital down-conversion (DDC) core allows designers to replace up to 16 specialist DDC ASIC devices with a single IP core for FPGA, significantly reducing board area, lowering power consumption, and increasing flexibility. The approach represents a major cost saving over traditional methods, with savings becoming more significant as the number of channels increases. ChannelCore64 is targeted at applications such as wireless base stations, satellite ground stations, and other multi-channel radio receivers.

Almost all radio receivers need to extract one or more relatively narrow channels from a much wider input spectrum in a process called down-conversion. The trend towards increased flexibility within this part of the system is enabling interoperability between different radio access technologies, permits dynamic reconfiguration of band-plans, and future-proofs investment in receiver systems. Furthermore, ever increasing user demand for bandwidth coupled with new technologies such as MIMO, means that systems must be capable of supporting an increasing number of channels.

ChannelCore64 utilises a unique approach to down-conversion that achieves massively greater silicon efficiency per channel than other FPGA-based DDC solutions, whilst providing all of the configuration controls that are typically associated with ASIC based DDCs. Furthermore, the end-to-end dynamic range offered by the core is significantly better than other available solutions, and a fractional re-sampler is included to allow output sample rates to be precisely configured.

The key features of ChannelCore64 are:

Support for two 16-bit ADC inputs each with a sample rate up to 200 mega-samples per second.

64 independent down-conversion channels, which may be connected to either ADC.

Independent tuning of channel centre frequencies with a resolution of < 0.01Hz.

Independent selection channel bandwidths.

Independent selection output sample rates with a resolution < 0.01Hz.

Channel reconfiguration when core is running without affecting the operation of other


A bit-true Matlab model is available free of charge which allows designers to accurately
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