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E2V Technologies - New 4-channel Gigahertz ADC

E2V Technologies : 30 May, 2007  (New Product)
World's first 4-channel Gigahertz ADC, incorporating data conversion rates of 5 Gsps, 2.5 Gsps and 1.25 Gsps with 8-bit resolution from a single chip at 1Watt per channel
e2v has announced the launch of the industry's first commercially available multi-channel 8-bit analogue-to-digital converter (ADC) capable of data conversion rates from 1.25 Gsps to 5 Gsps using e2v's unique data converter ‘multi-channel platform' architecture for Gigahertz applications. The EV8AQ160CTPY ADC is a monolithic chip featuring four separate digitally programmable 8-bit 1.25 Gsps ADC channels that when interleaved via an industry standard SPI (serial peripheral interface) and on-chip components; provide 2 channel x 2.5 Gsps or 1 channel x 5 Gsps data conversion rates.

Commercially available 8-bit Gigahertz ADCs are limited today to on-chip interleaving of 2 channels. Many 8-bit data converter applications however, incorporate 4 channels forcing designers to use off-chip components and programming to interleave two ADCs. The new ADC's ‘multi-channel platform' architecture sets a new standard in the industry by integrating on-chip interleaving adjustments of gain, offset and phase of 2x2 or 1x4 channels thus eliminating the added complexity and short-comings of interleaving multiple ADCs to provide higher data rates. It offers a unique feature of selecting the analogue input bandwidth (4 settings available from 600 MHz to 2.5 GHz). In fact, this latest ADC from e2v offers over 1000 operating modes, allowing designers unprecedented flexibility.

The benefits to designers include unbeatable flexibility in receiver design, seamless upgrades using the same ADC (and board lay-out) and impressive Gigahertz performance for applications such as test & measurement equipment, digital oscilloscopes, defence, satellite modems, wireless telecom and medical applications.

1, 2 or 4 analogue inputs are digitized via e2v's unique on-chip 4x4 cross-point switch (analogue MUX), independent ADC cores and selectable ratio DMUXs to offer dynamic performances of 52 dBc SFDR, 48dB SNR and 7.5 bit ENOB operating in 4-channel mode (at 1.25 Gsps) and 51 dBc SFDR, 44 dB SNR and 7.1 bit ENOB (effective number of bits) operating in 1-channel mode (at 5Gsps). BER (bit error rate) of 10-16 (at full date rate of 1.25 Gsps) and channel to channel isolation of 70 dB. All ADC modes of operation are using a single source 2.5 GHz differential symmetrical clock input.

Power consumption is a modest 980mW per channel with 3.3V (analogue) and 1.8V (outputs, digital) power supplies. Inputs are differential (50 Ohm) DC coupled with a selectable analogue input voltage swing (500 or 625 mVpp) relaxing the input amplifier requirements. Outputs are differential (50 Ohm) LVDS compatible with DDR (double data rate) for output clock speed flexibility.

'This new ADC pushes the boundaries in terms of design flexibility, user-friendly digital programming and market leading performance' said Andrew Benn, Product Marketing Manager for e2v's Broadband Data Conversion product line. 'This ADC reaffirms e2v's commitment to enabling designers to maximize system performance while lowering system design complexity and cost'.

The EV8AQ160CTPY is the first in a family of multi-channel ADCs; delivered in a EBGA380 RoHS plastic package and offered in Commercial temperature range. Samples and evaluation boards are available now with production quantities available in Q2 2008.

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